1. Field of the Invention
The invention relates in general to a memory and a method for fabricating the same, and more particularly to a NAND type dual bit nitride read only memory (also called N-bit) and a method for fabricating the same, that a process sequence is fully compatible with a complementary metal-oxide semiconductor (CMOS) process.
2. Description of the Related Art
N-bits (nitride read only memory) can be classified as NOR type N-bit and NAND type N-bit. NOR type N-bit features in capacities of storing instructions, prompt execution, rapid reading, large memory cell area and small storage capacity. NOR type N-bit is mainly applied in mobile phones, optical disk drives, hard disks and printers. NAND type N-bit features in data storage but not instruction storage. Also, the NAND type N-bit has small area and large storage capacity. The main application of the NAND type N-bit is in memory card of electronic products, such as MP3 players, digital cameras, digital video recorders, mobile phones, and the like.
With reference to FIGS. 1A and 1B simultaneously, FIG. 1A is a vertical view of a part of a conventional NOR type dual bit N-bit, while FIG. 1B is a cross-sectional view along hatches of 1B to 1B′ of FIG. 1A of a NOR type dual bit N-bit. In FIGS. 1A and 1B, a NOR type dual bit N-bit 30 includes at least a silicon substrate 10, a plurality of buried bit lines 20, a plurality of word lines 24, a plurality of oxide-nitride-oxide (ONO) stack structures 17, a plurality of barrier diffusion oxide 22, a plurality of memory cells 32, which are large dotted-line ranges of FIG. 1A and FIG. 1B, a plurality of first bit storage nodes 34, and a plurality of second bit storage cells 36, which are small dotted-line ranges of FIG. 1A and FIG. 1B.
In FIG. 1A, the buried bit lines 20 are formed in a spaced and parallel manner in the substrate 10, and the word lines 24 are also formed in a spaced and parallel manner above the substrate 10. The word lines 24 are perpendicular to the buried bit lines 20. In FIG. 1B, the ONO stack structures 17 is located between each of the word lines 24 and the substrate 10. Each of the ONO stack structure 17 includes a bottom oxide layer 11, a silicon nitride (SiN) layer 13, and a top oxide layer 15 from the below to the top. In addition, the barrier diffusion oxide 22 are formed above the buried bit lines 20 to isolate the word lines 24.
The memory cells 32 are formed by the word lines 24, the buried bit lines 20, and the ONO stack structures 17. The memory cells 32 form as a cell array as shown in FIG. 1A. Each of the memory cells 32 includes the first bit storage nodes 34 and the second bit storage nodes 36. The first bit storage nodes 34 and the second bit storage nodes 36 of every memory cell 32 are spaced at intervals along an extension direction of the word lines 24, so that the area of every memory cell 32 can be larger.
Referring to FIG. 2A to FIG. 2E, a cross-sectional view of procedures of a fabricating method for a NOR type dual bit N-bit of FIG. 1B is shown. Firstly, the silicon substrate 10 is provided and an ONO layer 16 is formed on the silicon substrate 10. The ONO layer 16 includes the bottom oxide layer 11, the silicon nitride (SiN) layer 13, and the top oxide layer 15 from the below to the top in order. Subsequently, a patterned photoresist layer 18 is formed on the ONO layer 16. And also the spaced and parallel buried bit lines 20 are formed by utilizing an ion implantation process. The buried bit lines 20 are formed in the silicon substrate 10, which is not covered by the patterned photoresist layer 18 as shown in FIG. 2B. Ion implantation is applied to form the buried bit lines 20, which includes the steps of: increasing the energy or kinetic energy of the dopant and implanting the dopant to the silicon substrate 10 through the ONO layer 16.
Next, the exposed part of the top oxide layer 15 and the silicon nitride (SiN) layer 13 thereunder is removed, and also the patterned photoresist layer 18 is removed as shown in FIG. 2C. Sequentially, the barrier diffusion oxide 22 are formed on the buried bit lines 20, and the barrier diffusion oxide 22 partitions the remaining ONO layer 16 into several ONO stack structures 17 as shown in FIG. 2D. And then the spaced word lines 24 perpendicular to the buried bit lines 20 are formed on the ONO stack structures 17, so that the NOR type dual bit N-bit 30 is accomplished, as shown in FIG. 2E. In a step of forming the word lines 24, a polysilicon layer can be formed on the silicon substrate 10 first, and then a part of the polysilicon layer is removed by photolithography and etching, so as to form the word lines 24.
Because the barrier diffusion oxide 22 and the word lines 24 are completed by thermal process, and also the buried bit lines 20 is formed prior to the formation of the barrier diffusion oxide 22 and the word lines 24, the ion dopant of the buried bit lines 20 tends to diffuse during and after the thermal process. Thereby the concentration of the ion dopant of the buried bit lines 20 differs from the original. The electricity quality of the NOR type N-bit 30 is consequently influenced.